Engineering - Electrical, Recent advances in semiconductor technology offer vertical interconnect access (via) that extends through silicon, popularly known as through silicon vias (TSVs). This book provides a comprehensive, review of the theory behind TSVs while covering most recent advancements in materials, models, and designs. It also presents various aspects of using graphene-based filler materials in TSVs for future three-dimensional integrated circuits (3D ICs). The structure of advanced 3D packaging technology and its electrical equivalent model are thoroughly discussed as well. The fabrication techniques of various filler material-based TSVs are provided along with the pros and cons of different filler materials such as copper, carbon nanotube (CNT), and graphene nanoribbon (GNR). Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for Cu-, CNT-, and GNR-based TSVs are presented. The book develops a strong foundation for readers to understand the need for moving from conventional materials towards graphene-based filler materials in TSVs. Book jacket.