Free shipping on orders over $99
Compiling Parallel Loops for High Performance Computers

Compiling Parallel Loops for High Performance Computers

Partitioning, Data Assignment and Remapping

by David E. Hudak and Santosh G. Abraham
Hardback
Publication Date: 31/10/1992

Share This Book:

  $169.00
or 4 easy payments of $42.25 with
afterpay
This item qualifies your order for FREE DELIVERY
The exploitation of parallel processing to improve computing speeds is being examined at virtually all levels of computer science, from the study of parallel algorithms to the development of microarchitectures which employ multiple functional units. The most visible aspect of this interest in parallel processing is the commercially available multiprocessor systems which have appeared in the past decade. Unfortunately, the lack of adequate software support for the development of scientific applications that will run efficiently on multiple processors has stunted the acceptance of such systems. One of the major impediments to achieving high parallel efficiency on many data-parallel scientific applications is communications overhead, which is exemplified by cache coherency traffic and global memory accesses. This book presents compile-time techniques to reduce the overhead of interprocessors with a logically shared address space and physically distributed memory. Such techniques can be used by scientific application designers seeking to optimize code for a particular high-performance computer.
In addition, these techniques can be seen as a necessary step toward developing software to support efficient parallel programmes. In multiprocessor systems with physically distributed memory, reducing communication overhead involves both data partitioning and data placement. "Adaptive Data Partitioning" (ADP) reduces the execution time of parallel programmes by minimizing interprocessor communication for iterative data-parallel loops with near-neighbour communication. Data placement schemes are presented that reduce communication overhead. Under the loop partition specified by ADP, global data is partitioned into classes for each processor, allowing each processor to cache certain regions of the global data set. In addition, for many scientific applications, peak parallel efficiency is achieved only when machine-specific tradeoffs between load imbalance and communication are evaluated and utilized in choosing the data partition. The techniques in this book evaluate these tradeoffs to generate optimum cyclic partitions for data-parallel loops with either a linearly varying or uniform computational structure and either neighbourhood or dimensional multicast communication patterns.
This tradeoff is also treated within the CPR (Collective Partitioning and Remapping) algorithm, which partitions a collection of loops with various computational structures and communication patterns. Experiments that demonstrate the advantage of ADP, data placement, cyclic partitioning and CPR were conducted on the Encore Multimax and BBN TC2000 multiprocessors using the ADAPT system, a programme partitioner which automatically restructures iterative data-aparallel loops.
ISBN:
9780792392835
9780792392835
Category:
Computer architecture & logic design
Format:
Hardback
Publication Date:
31-10-1992
Language:
English
Publisher:
Kluwer Academic Publishers
Country of origin:
United States
Pages:
159
Dimensions (mm):
235x155x11mm
Weight:
0.96kg

This title is in stock with our Australian supplier and should arrive at our Sydney warehouse within 1 - 2 weeks of you placing an order.

Once received into our warehouse we will despatch it to you with a Shipping Notification which includes online tracking.

Please check the estimated delivery times below for your region, for after your order is despatched from our warehouse:

ACT Metro: 2 working days
NSW Metro: 2 working days
NSW Rural: 2-3 working days
NSW Remote: 2-5 working days
NT Metro: 3-6 working days
NT Remote: 4-10 working days
QLD Metro: 2-4 working days
QLD Rural: 2-5 working days
QLD Remote: 2-7 working days
SA Metro: 2-5 working days
SA Rural: 3-6 working days
SA Remote: 3-7 working days
TAS Metro: 3-6 working days
TAS Rural: 3-6 working days
VIC Metro: 2-3 working days
VIC Rural: 2-4 working days
VIC Remote: 2-5 working days
WA Metro: 3-6 working days
WA Rural: 4-8 working days
WA Remote: 4-12 working days

Reviews

Be the first to review Compiling Parallel Loops for High Performance Computers.