7 1/2 X 9 1/4 in Chapter 1 Alternative FPGA Architectures
1.1 A word of warn ing
1.2 A little background information
1.3 An tifuse versus SRAM versus ?
1.4 Fine-, medium-, and coarse- grained architectures
1.5 MUX- versus LUT-based logic block s
1.6 CLBs versus LABs versus slices
1.7 Fast carry chains
1.8 Embedded RAMs
1.9 Embedded mu ltipliers, adders, MACs, etc.
1.10 Embedded processor cores (hard and soft)
1.11 Clock trees and clock managers
1.12 General-purpose I/O
1.13 Gigabit transceivers1.14 Hard IP, soft IP, and firm IP
1.15 System gates versus real gates
1.16 FPGA years

Chapter 2 Design Techniques, Rules, and Guidelines
2.1 Hardware Description Languages
2.2 Top-Down Design
2.3 Synchronous Design
2.4 Floating Nodes
2.5 Bus Contention
2.6 One-Hot State Encoding
2.7 Design For Test (DFT)
2.8 Testing Redundant Logic<