This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime.











Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing;
Describes automated compilation of programmable logic-in-memory computer architectures;
Includes several effective optimization algorithm also applicable to classical logic synthesis;
Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.