Free shipping on orders over $99
Verilog HDL Design Examples

Verilog HDL Design Examples

by Joseph Cavanagh
Hardback
Publication Date: 17/10/2017

Share This Book:

14%
OFF
RRP  $389.00

RRP means 'Recommended Retail Price' and is the price our supplier recommends to retailers that the product be offered for sale. It does not necessarily mean the product has been offered or sold at the RRP by us or anyone else.

$337.75
or 4 easy payments of $84.44 with
afterpay
    Please Note: We will source your item through a special order. Generally sent within 120 days.
This item qualifies your order for FREE DELIVERY
The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles-including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs).
ISBN:
9781138099951
9781138099951
Category:
Information technology: general issues
Format:
Hardback
Publication Date:
17-10-2017
Publisher:
Taylor & Francis Ltd
Country of origin:
United Kingdom
Pages:
674
Dimensions (mm):
254x178mm
Weight:
1.39kg

Our Australian supplier has this title on order. You can place a backorder for this title now and we will ship it to you when it becomes available. 

While we are unable to provide a delivery estimate, most backorders will be delivered within 120 days. If we are informed by our supplier that the title is no longer available during this time, we will cancel and refund you for this item.  Likewise, if no delivery estimate has been provided within 120 days, we will contact our supplier for an update.  If there is still no delivery estimate we will then cancel the item and provided you with a refund.

If we are able to secure you a copy of the title, our supplier will despatch it to our Sydney warehouse.  Once received we make sure it is in perfect condition and then despatch it to you via the Australia Post eParcel service, which includes online tracking.  You will receive a shipping notice from us when this occurs.

Reviews

Be the first to review Verilog HDL Design Examples.